A serial interface protocol, such as the SATA protocol, can have more signaling latency than desired. One aspect of the signaling latency in the SATA protocol is associated with the latency to process link layer primitives, such as processing the X_RDY and R_RDY primitives. In the SATA protocol, there is an exchange of information between a host and the device through Frame Information Structures (FIS). Each FIS includes a group of Dwords. SATA utilizes primitives for control purposes and also to provide status information. Each primitive is also made up of one Dword. The primitives are also used to perform handshaking between a host and a device.
The SATA specification defines a physical layer, a link layer, and a transport layer. The physical layer defines electrical and physical characteristics. The physical layer (PHY) includes a transmit and receive pair. The physical line encoding system uses 8b/10b encoding. After the physical layer has established a link, the link layer is responsible for transmission and reception of Frame Information Structures (FIS) over the SATA link. The FIS packets contain control information or payload data. The link layer additionally manages the flow control for the link The transport layer acts on the frame, and transmits and receives frames in an appropriate sequence.
The signals in the SATA cable are arranged in 2 pairs—one pair for transmit data (TX+ & TX−), the other for receive data (RX+ & RX−). The serial data stream is capable of transmission at 1.5, 3.0 and 6.0 GT/s (Giga transfers/sec).
In a SATA interface, the binary data is encoded using the commonly known 8b/10b encoding. This is where, as the name suggests, 8 bits of data are converted to 10 bit symbols for transmission. There are two main reasons for doing this, the first is to maintain the DC balance of the transmitted signal, and the second is to ensure continuous bit transitions in order to recover a clock from the received signal. The DC balance is achieved by having the difference between the number of transmitted ‘1’s and number of transmitted ‘0’s (a figure termed the ‘disparity’) in any sequence of 20 bits or more not exceed two, also the number of ‘1’s or ‘0’s in a row may not exceed 5.
According to the above, the result is that the long term ratio of ‘2’s to ‘0’s tends towards exactly 50% and at the end of each symbol. The difference (disparity) is either +1 or −1.
FIG. 1 illustrates aspects of the encoding of a SATA interface. As shown in FIG. 1, the 8 information bits (conventionally labeled A, B, C, and D . . . to H) plus a control variable Z (Z has the value D if the information byte is a data byte, or K if the information byte is a control character byte). The lower 5 bits of the data E-A are grouped together, and the top 3 bits H-F are separately grouped. Then, the groupings are interchanged so that bits E-A become the most significant, and the bits H-F the least significant. The encoding is now in the form Zxx.y (xx=decimal form of EDCBA; and y is a decimal form of HGF). Now the data is transformed, with the top 5 bits E-A transformed into a 6 bit symbol and 3 bits H-F into a 4 bit symbol, to form the complete 10 bit symbol, with bits a, b, c . . . h, i, j in the order they are transmitted (least significant first).
Each of the individual 6 and 4 bit codes has either equal ‘1’s and “0’s (zero disparity), but since there are not enough of these codes available, some codes either have 1 excess ‘1’s or 1 excess ‘0’s (disparity of +2 and −2 respectively). Which code is chosen depends on the current value (prior to the sending of this symbol) of running disparity, which starts at an initial −1. If the current value is −1, the symbol with +2 disparity is chosen; if the current value is +1, the symbol with −2 disparity is chosen. This means that the running disparity at any time will either be −1 or +1 (given that symbols with disparity of 0 can also appear in the stream).
The following table shows the allocation of 6 bit code symbols:
TABLE 5b/6bInputRD = −1RD = +1InputRD = −1RD = +1EDCBAabcdeiEDCBAabcdeiD.0000000100111011000D.1610000011011100100D.0100001011101100010D.1710001100011D.0200010101101010010D.1810010010011D.0300011110001D.1910011110010D.040010011010101010D.2010100001011D.0500101101001D.2110101101010D.0600110011001D.2210110011010D.0700111111000000111D.2310111111010000101D.0801000111001000110D.2411000110011001100D.0901001100101D.2511001100110D.1001010010101D.2611010010110D.1101011110100D.2711011110110001001D.1201100001101D.2811100001110D.1301101101100D.2911101101110010001D.1401110011100D.3011110011110100001D.1501111010111101000D.3111111101011010100K.2811100001111110000
The following table shows the allocation of 4 bit code symbols:
TABLE 3b/4bInputRD = −1RD = +1InputRD = −1RD = +1HGFfghjHGFfghjD.xx.000010110100K.xx.000010110100D.xx.10011001K.xx.100101101001D.xx.20100101K.xx.201010100101D.xx.301111000011K.xx.301111000011D.xx.410011010010K.xx.410011010010D.xx.51011010K.xx.510101011010D.xx.61100110K.xx.611010010110D.xx.P711111100001D.xx.A711101111000K.xx.711101111000
The control symbols are chosen as 10 bit symbols which are valid code symbols but which do not have a corresponding 8 bit data byte.
The link layer handles the protocol for sending and receiving data payloads and the encapsulation of data. Data bytes Dxx.y are encoded using 8b/10b as described above and link layer primitives are used to control the sending and receiving of data. These primitives are 4 bytes (a DWord of 32 bits) and all start with the control character K28.3, except for the ALIGN primitive which starts with K28.5. Data is sent in frames in a Frame Information Structure (FIS). A request to send an FIS is initiated by sending the X_RDY primitive, and once the receiver decodes and recognizes this primitive it responds with R_RDY to indicate it is ready to receive the frame, which, when the originator decodes and recognizes its receipt, proceeds to the next phase of the protocol.
FIG. 2 illustrates aspects of performing FIS transfers over a SATA interface. For each FIS transfer therefore, there is a latency associated with sending each FIS as shown in FIG. 2. At the FIS originator 200, prior to the FIS being sent, the X_RDY primitive is prepared by the link layer transmit section 220, then passed to the transmit physical layer 222 and through the cable transmit pair 240 to the FIS receiver 210. The signal is received through the physical layer 230 and deserialized and passed to the receive link layer 232 where 8b/10b decoding, descrambling and error checking performed before being handled by the link layer protocol state machine 250. This recognizes the receipt of X_RDY which causes the state machine to respond and send the R_RDY primitive. This passes through the transmit link 234 and PHY 236 layers through the cable pair 260 where the FIS originator performs the reciprocal receive PHY 224 and link layer 226 processing to deserialize then performs 8b/10b decoding, descrambling, and error checking before the R-RDY is finally recognized and the FIS transfer may proceed. The in/out latency at the receiving end 270 is of the order of 20 DWord time periods and a similar out/in latency 280 at the FIS originator.
For each data transfer, there are 5 separate FIS transfers involved in the SATA protocol:
1. Host to Device FIS (command)
2. Device to Host FIS (accept)
3. DMA Setup FIS (start data transfer)
4. Data transfer FIS (read or write data dwords)
5. Set Device Bits FIS (report status)
It is possible that the status reports may be aggregated, such that one set of device bits FIS can report the status for some number N of separate data transfers. This reduces the overhead to 4 FIS transfers plus a fraction of an FIS transfer (shared between the aggregated transfers) per data transfer.
FIG. 3 shows the basic operation of a SATA PHY (physical) 100 and link layer in the processing of FIS transfers. The basic operation is shown of a SATA PHY (physical) layer 300 and link layer 320 in the processing of FIS transfers. Incoming data from the serial cable link on the RX− and RX+ differential signals 310 is passed to differential receivers and is then converted from serial to parallel in the deserializer 305. The resulting 20 bit parallel data 315 is passed to the link layer 320 where 8b/10b decoding, FIS data unscrambling and CRC checking are performed 325. The 16 bit parallel data 327 with associated K code/Data indicator bits 328 are fed to a demultimplexer 330 where primitives 332 are separated from FIS frames 331. The FIS frames are sent to a receive buffer, and the primitives 332 to the receive state machine 335, which controls 333 the operation of demultiplexing.
Outgoing data is sent under the control of the transmit state machine 340 which multiplexes 345 the FIS frames 343 from the transmit buffer and primitives 342 from the state machines under control 341 of the state machine. The multiplex parallel data 347 and K code/Data indicator bits 348 are passed to link layer encoding 350, where CRC bits are generated, FIS frame data is scrambled and 8b/10b encoding is applied. The resultant 20 bit parallel data 365 is passed to the PHY serializer and differential driver 360 where the data is serialized and sent to differential drivers to the transmit differential pair TX− and TX+ 370 on the serial cable link.
As previously discussed, a SATA interface has a large signaling latency. Each FIS transfer suffers this signaling latency. The in/out latency at the receiving end is of the order of 20 DWord time periods and a similar out/in at the FIS originator. Attempts to reduce this latency in the prior art are unsatisfactory and not compatible with commercial applications that require robustness.
In many commercial applications, signaling latency cannot be reduced at the cost of eliminating features of the SATA interface that are required for robustness. For example, US 2004/0010625 to Lo et al. (hereinafter “Lo”), describes a method to reduce latency by using a fixed pattern generator in the physical layer. As described in the Abstract of Lo, a physical layer controller directly returns the primitive formats to an output device without sending or receiving the primitive formats to the link layer. The approach of Lo suffers from several drawbacks, including the fact that it renders inoperative features of a SATA interface required to have a robust connection.
In Lo, the link layer is not kept informed about the primitives received or transmitted, such that the interface of Lo is not able to correctly handle any errors or abnormal conditions such as the sending of a reset by the originator to abort the transfer. If an out of sequence response occurs, such as a reset, the approach of Lo will cause the SATA protocol to fail as the link layer is not tracking the state of the communication protocol, and thus not implementing the state changes required for robust communications. This can result in a complete break in communications, which in unacceptable in most commercial applications.
Therefore, in view of these problems in the prior art, an improved technique to reduce latency while permitting the detection and handling of errors and abnormal conditions was developed.